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MT8885
(R)
Integrated DTMF Transceiver with Power Down & Adaptive Micro Interface Advance Information
Features
* * * * * * * * External power down pin Central office quality DTMF transmitter/ receiver Low power consumption High speed adaptive micro interface Adjustable guard time Automatic tone burst mode Call progress tone detection to -30dBm DTMF transmitter/receiver power down via register control
ISSUE 1
May 1995
Ordering Information MT8885AE MT8885AN MT8885AP -40C to 24 Pin Plastic DIP 24 Pin SSOP 28 Pin PLCC +85C
Applications
* * * * * Credit card systems Paging systems Repeater systems/mobile radio Interconnect dialers Personal computers
The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones. The MT8885 utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. The MT8885 provides enhanced power down features. The transmitter and receiver may independently be powered down via register control. A full chip power down pin provides simple power and control capability.
Description
The MT8885 is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability.
TONE
D/A Converters
Row and Column Counters
Transmit Data Register Status Register
Data Bus Buffer
D0 D1 D2 D3
Tone Burst Gating Cct. IN+ INGS OSC1 OSC2 Oscillator Circuit Bias Circuit + Dial Tone Filter
Control Logic
Interrupt Logic IRQ/CP
High Group Filter Low Group Filter Control Logic
Digital Algorithm and Code Converter
Control Register A Control Register B I/O Control
DS/RD CS R/W/WR RS0
Steering Logic
Receive Data Register
VDD VRef
VSS
PWDN
ESt
St/GT
Figure 1 - Functional Block Diagram
4-51
MT8885
IN+ INGS VRef VSS OSC1 OSC2 NC NC TONE R/W/WR CS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD St/GT ESt D3 D2 D1 D0 NC PWDN IRQ/CP DS/RD RS0 GS NC ININ+ VDD St/GT ESt 5 6 7 8 9 10 11 4 3 2 1 28 27 26 *
Advance Information
24 PIN DIP/SSOP
Figure 2 - Pin Connections
Pin Description
Pin # 24 1 2 3 4 5 6 7 10 11 12 13 14 15 28 1 2 4 6 7 8 9 12 14 15 17 18 Name IN+ INGS VRef VSS OSC1 OSC2 TONE CS RS0 Non-inverting op-amp input. Inverting op-amp input. Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference Voltage output (VDD/2). Ground (0V). Oscillator input. This pin can also be driven directly by an external clock. Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally. Output from internal DTMF transmitter. Chip Select input. This signal must be qualified externally by either address strobe (AS), valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12. Register Select input. Refer to Table 3 for bit interpretation. CMOS compatible. Description
13 R/W(WR) (Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible.
DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only required when the device is being accessed. CMOS compatible. IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes low when a valid DTMF tone burst has been transmitted or received. In call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter, see Figure 8. PWDN Power Down (input). Active High. Powers down the device and inhibits the oscillator. IRQ and TONE output are high impedance. Data bus is held in tri-state. This pin is internally pulled down. Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1 (Intel). TTL compatible. Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply (5V typ.).
16
19
14- 1817 21 18 22
D0-D3 ESt
19
23
St/GT
20
4-52
24
VDD
TONE R/W/WR CS RS0 NC DS/RD IRQ/CP
12 13 14 15 16 17 18
NC VRef VSS OSC1 OSC2 NC NC
25 24 23 22 21 20 19
NC D3 D2 D1 D0 NC PWDN
28 PIN PLCC
Advance Information
Pin Description
Pin # 24 28
16, 20, 25
MT8885
Name NC No Connection.
Description
8,9 3,5, 17 10,11
Functional Description
The MT8885 Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected. The adaptive micro interface allows microcontrollers, such as the 68HC11, 80C51 and TMS370C50, to access the MT8885 internal registers.
Receiver Section
Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies (see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.
MT8885 IN+ IN-
Power Down
The MT8885 provides enhanced power down functionality to facilitate minimization of supply current consumption. DTMF transmitter and receiver circuit blocks may be independently powered down via register control. When asserted, the RxEN control bit powers down all analog and digital circuitry associated solely with the DTMF and Call Progress receiver. The TOUT control bit is used to disable the transmitter and put all circuitry associated only with the DTMF transmitter in power down mode. With the TOUT control bit asserted, the TONE output pin is held in a high impedance (floating) state. When both power down control bits are asserted, circuits utilized by both the DTMF transmitter and receiver are also powered down. This includes the crystal oscillators, and the VRef generator. In addition, the IRQ , TONE output and DATA pins are held in a high impedance state. Finally, the whole device is put in a power down state when the PWDN pin is asserted.
C
RIN
RF VOLTAGE GAIN (AV) = RF / RIN
GS VRef
Figure 3 - Single-Ended Input Configuration
MT8885 C1 R1 IN+ INC2 R4 R5 GS
Input Configuration
R3 R2 VRef DIFFERENTIAL INPUT AMPLIFIER C1 = C2 = 10 nF R1 = R4 = R5 = 100 k R2 = 60k, R3 = 37.5 k R3 = (R2R5)/(R2 + R5) VOLTAGE GAIN INPUT IMPEDANCE (AV diff) - R5/R1 (Z diff) = 2 R12 + (1/C)2
IN
The input arrangement of the MT8885 provides a differential-input operational amplifier as well as a bias source (VRef), which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in Figure 3. Figure 4 shows the necessary connections for a differential input configuration.
Figure 4 - Differential Input Configuration
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MT8885
FLOW FHIGH DIGIT D3 D2 D1 D0
Advance Information
(VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT output is activated and drives v c to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is active. The contents of the output latch are updated on an active delayed steering transition. This data is presented to the four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.
VDD
697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941
1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633
1 2 3 4 5 6 7 8 9 0 * # A B C D
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0= LOGIC LOW, 1= LOGIC HIGH
Table 1. Functional Encode/Decode Table Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the "signal condition" in some industry specifications) the "Early Steering" (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state.
MT8885 VDD St/GT ESt R1 C1 Vc
tGTA = (R1C1) In (VDD / VTSt) tGTP = (R1C1) In [VDD / (VDD-VTSt)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the following inequalities (see Figure 7): t REC t DPmax + t GTPmax - t DAmin t REC t DPmin + t GTPmin - t DAmax t ID t DAmax + t GTAmax - t DPmin t DO t DAmin + t GTAmin - t DPmax The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum
Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (tGTP), vc reaches the threshold
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Advance Information
signal duration to be recognized by the receiver. A value for C1 of 0.1 F is recommended for most
MT8885
applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independent tone present (tGTP) and tone absent (t GTA) guard times. This may be necessary to meet system specifications which place both accept and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. Alternatively, a relatively short t REC with a long t DO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in Figure 7 with a description of the events in Figure 9.
tGTP = (RPC1) In [VDD / (VDD-VTSt)] tGTA = (R1C1) In (VDD/VTSt) VDD C1 St/GT RP = (R1R2) / (R1 + R2)
R1 ESt
R2 a) decreasing tGTP; (tGTP < tGTA)
tGTP = (R1C1) In [VDD / (VDD-VTSt)] VDD C1 St/GT tGTA = (RpC1) In (VDD/VTSt) RP = (R1R2) / (R1 + R2)
Call Progress Filter
R1 R2 b) decreasing tGTA; (tGTP > tGTA)
ESt
Figure 6 - Guard Time Adjustment
A call progress mode, using the MT8885, can be selected allowing the detection of various tones, which identify the progress of a telephone call on the network. The call progress tone input and DTMF input are common, however, call progress tones can only be detected when CP mode has been selected.
C D E F
EVENTS
A
B
tREC
Vin
tREC
TONE #n
tID
TONE #n + 1
tDO
TONE #n + 1
tDP
ESt
tDA tGTP tGTA
VTSt
St/GT
tPStRX
RX0-RX3 DECODED TONE # (n-1) #n # (n + 1)
tPStb3
b3
b2
Read Status Register IRQ/CP
Figure 7 - Receiver Timing Diagram
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MT8885
Advance Information
EXPLANATION OF EVENTS A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR. D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED. F) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR. EXPLANATION OF SYMBOLS DTMF COMPOSITE INPUT SIGNAL. Vin ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. RX0 -RX3 4-BIT DECODED DATA IN RECEIVE DATA REGISTER b3 DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A VALID DTMF SIGNAL. b2 INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS REGISTER IS READ. INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS IRQ/CP CLEARED AFTER THE STATUS REGISTER IS READ. tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. tREC MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS. tID MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL. tDO TIME TO DETECT VALID FREQUENCIES PRESENT. tDP TIME TO DETECT VALID FREQUENCIES ABSENT. tDA GUARD TIME, TONE PRESENT. tGTP GUARD TIME, TONE ABSENT. tGTA
Figure 9 - Description of Timing Events DTMF signals cannot be detected if CP mode has been selected (see Table 7). Figure 8 indicates the useful detect bandwidth of the call progress filter. Frequencies presented to the input, which are within the `accept' bandwidth limits of the filter, are hardlimited by a high gain comparator with the IRQ/CP pin serving as the output. The squarewave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. Frequencies which are in the `reject' area will not be detected and consequently the IRQ/CP pin will remain low. the transmit Data Register. Note that this is the same as the receiver output code. The individual tones which are generated (fLOW and fHIGH) are referred to as Low Group and High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB to com-pensate for high group attenuation on long loops.
LEVEL (dBm)
DTMF Generator
The DTMF transmitter employed in the MT8885 is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in Table 1 must be written to
4-56 -25
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
0 = Reject
250
500
750
FREQUENCY (Hz)
= May Accept AAAAAAAAAA AAAAAAAAAA = Accept AAAAAAAAAA AAAAAAAAAA
Figure 8 - Call Progress Response
Advance Information
MT8885
Scaling Information 10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz
Figure 10 - Spectrum Plot The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time segments is fixed at 32, however, by varying the segment length as described above the frequency can also be varied. The divider output clocks another counter, which addresses the sinewave lookup ROM. The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which are then mixed using a low noise summing amplifier. The oscillator described needs no "start-up" time as in other DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can be seen from Figure 6 that the distortion products are very low in amplitude. application or by any one of the exchange transmitter specifications currently existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms1 ms which is a standard interval for autodialer and central office applications. After the burst/pause has been issued, the appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode) is selected, the burst/pause duration is doubled to 102 ms 2 ms. Note that when CP mode and Burst mode have been selected, DTMF tones may be transmitted only and not received. In applications where a non-standard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and disabling the transmitter.
Single Tone Generation
A single tone mode is available whereby individual tones from the low group or high group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion measurements. Refer to Control Register B description for details.
Burst Mode
In certain telephony applications it is required that DTMF signals being generated are of a specific duration determined either by the particular
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MT8885
ACTIVE INPUT L1 L2 L3 L4 H1 H2 H3 H4 OUTPUT FREQUENCY (Hz) SPECIFIED ACTUAL %ERROR
Advance Information
DTMF Clock Circuit
+0.30 -0.49 -0.54 +0.74 +0.57 -0.32 -0.35 +0.73
MT8885 OSC1 OSC2 MT8885 OSC1 OSC2 MT8885 OSC1 OSC2
697 770 852 941 1209 1336 1477 1633
699.1 766.2 847.4 948.0 1215.9 1331.7 1471.9 1645.0
The internal clock circuit is completed with the addition of a standard television colour burst crystal having a resonant frequency of 3.579545 MHz. A number of MT8885 devices can be connected as shown in Figure 11 such that only one crystal is required. Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left unconnected.
Table 2. Actual Frequencies Versus Standard Requirements
Distortion Calculations
The MT8885 is capable of producing precise tone bursts with minimal error in frequency (see Table 2). The internal summing amplifier is followed by a firstorder lowpass switched capacitor filter to minimize harmonic components and intermodulation products. The total harmonic distortion for a single tone can be calculated using Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage.
3.579545 MHz
Figure 11 - Common Crystal Connection
Microprocessor Interface
The MT8885 design incorporates an adaptive interface, which allows it to be connected to various kinds of microprocessors. Key functions of this interface include the following: * Continuous activity on DS/RD is not necessary to update the internal status registers. senses whether input timing is that of an Intel or Motorola controller by monitoring the DS (RD), R/W (WR) and CS inputs. generates equivalent CS signal for internal operation for all processors. differentiates between multiplexed and nonmultiplexed microprocessor buses. Address and data are latched in accordingly. compatible with Motorola and Intel processors.
V22f + V23f + V24f + .... V2nf
THD (%) = 100
Vfundamental
*
Equation 1. THD (%) For a Single Tone The Fourier components of the tone output correspond to V2f.... Vnf as measured on the output waveform. The total harmonic distortion for a dual tone can be calculated using Equation 2. VL and V H correspond to the low group amplitude and high group amplitude, respectively and V 2IMD is the sum of all the intermodulation components. The internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as shown in Figure 10. *
*
*
V22L + V23L + .... V2nL + V22H + V23H + .. V2nH + V2IMD
THD (%) = 100
V2L + V2H
Equation 2. THD (%) For a Dual Tone
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Figure 16 shows the timing diagram for Motorola microprocessors with separate address and data buses. Members of this microprocessor family include 2 MHz versions of the MC6800, MC6802 and MC6809. For the MC6809, the chip select (CS) input signal is formed by NANDing the (E+Q) clocks and address decode output. For the MC6800 and MC6802, CS is formed by NANDing VMA and address decode output. On the falling edge of CS, the internal logic senses the state of data strobe
Advance Information
(DS). When DS is low, Motorola processor operation is selected. Figure 17 shows the timing diagram for the Motorola MC68HC11 (1 MHz) microcontroller. The chip select (CS) input is formed by NANDing address strobe (AS) and address decode output. Again, the MT8885 examines the state of DS on the falling edge of CS to determine if the micro has a Motorola bus (when DS is low). Additionally, the Texas Instruments TMS370CX5X is qualified to have a Motorola interface. Figure 12(a) summarizes connection of these Motorola processors to the MT8885 DTMF transceiver. Figures 18 and 19 are the timing diagrams for the Intel 8031/8051 (12 MHz) and 8085 (5 MHz) microcontrollers with multiplexed address and data buses. The MT8885 latches in the state of RD on the falling edge of CS. When RD is high, Intel processor operation is selected. By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS can be generated. Figure 12(b) summarizes the connection of these Intel processors to the MT8885 transceiver. NOTE: The adaptive micro interface relies on highto-low transition on CS to recognize the microcontroller interface and this pin must not be tied permanently low.
MT8885
The adaptive micro interface provides access to five internal registers. The read-only Receive Data Register contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is accomplished with two control registers (see Tables 6 and 7), CRA and CRB, which have the same address. A write operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-only status register indicates the current transceiver state (see Table 8). A software reset must be included at the beginning of all programs to initialize the control registers upon power-up or power reset (see Figure 14). Refer to Tables 4-7 for bit descriptions of the two control registers. The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a square-wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external pull-up resistor (see Figure 13).
MC6800/6802 A0-A15
MT8885
MC68HC11 A8-A15 AS AD0-AD3 DS RW
MT8885 CS D0-D3 RS0 DS/RD R/W/WR
CS RS0
VMA D0-D3 RW 2 (a) D0-D3 R/W/WR DS/RD
MC6809
MT8885
8031/8051 8080/8085
MT8885
A0-A15
CS RS0
A8-A15
CS D0-D3 RS0 DS/RD R/W/WR (b)
Q E D0-D3 R/W
ALE D0-D3 R/W/WR DS/RD P0 RD WR
Figure 12 a) & b) - MT8885 Interface Connections for Various Intel and Motorola Micros
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MT8885
Advance Information
Motorola RS0 R/W
Intel WR RD FUNCTION Write to Transmit Data Register Read from Receive Data Register Write to Control Register Read from Status Register
0 0 1 1
0 1 0 1
0 1 0 1
1 0 1 0
Table 3. Internal Register Functions
b3 RSEL
b2 IRQ
b1 CP/DTMF
b0 TOUT
Table 4. CRA Bit Positions
b3 C/R
b2 S/D
b1 TEST
b0 BURST ENABLE
Table 5. CRB Bit Positions
BIT b0
NAME TOUT
DESCRIPTION Tone Output Control. A logic high enables the tone output; a logic low turns the tone output off and places the complete DTMF transmitter circuit in power down mode. This bit controls all transmit tone functions. Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode; a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and transmitting DTMF signals. In CP mode a retangular wave representation of the received tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control register A, b2=1). In order to be detected, CP signals must be within the bandwidth specified in the AC Electrical Characteristics for Call Progress. Note: DTMF signals cannot be detected when CP mode is selected. Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the interrupt function. When IRQ is enabled and DTMF mode is selected (control register A, b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been received for a valid guard time duration, or 2) the transmitter is ready for more data (burst mode only). Register Select. A logic high selects control register B for the next write cycle to the control register address. After writing to control register B, the following control register write cycle will be directed to control register A. Table 6. Control Register A Description
b1
CP/DTMF
b2
IRQ
b3
RSEL
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Advance Information
MT8885
DESCRIPTION
BIT b0
NAME BURST
Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode. When activated, the digital code representing a DTMF signal (see Table 1) can be written to the transmit register, which will result in a transmit DTMF tone burst and pause of equal durations (typically 51 msec). Following the pause, the status register will be updated (b1 Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been enabled. When CP mode (control register A, b1) is enabled the normal tone burst and pause durations are extended from a typical duration of 51 msec to 102 msec. When BURST is high (de-activated) the transmit tone burst duration is determined by the TOUT bit (control register A, b0).
b1 b2
RxEN S/D
This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both circuits. A logic high deactivates and puts both receiver circuits into power down mode. Single or Dual Tone Generation. A logic high selects the single tone output; a logic low selects the dual tone (DTMF) output. The single tone generation function requires further selection of either the row or column tones (low or high group) through the C/R bit (control register B, b3). Column or Row Tone Select. A logic high selects a column tone output; a logic low selects a row tone output. This function is used in conjunction with the S/D bit (control register B, b2). Table 7. Control Register B Description
b3
C/R
BIT b0 b1
NAME IRQ TRANSMIT DATA REGISTER EMPTY (BURST MODE ONLY) RECEIVE DATA REGISTER FULL DELAYED STEERING
STATUS FLAG SET Interrupt has occurred. Bit one (b1) or bit two (b2) is set. Pause duration has terminated and transmitter is ready for new data. Valid data is in the Receive Data Register. Set upon the valid detection of the absence of a DTMF signal.
STATUS FLAG CLEARED Interrupt is inactive. Cleared after Status Register is read. Cleared after Status Register is read or when in non-burst mode. Cleared after Status Register is read. Cleared upon the detection of a valid DTMF signal.
b2 b3
Table 8. Status Register Description
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MT8885
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VDD MT8885 C1 DTMF/CP INPUT R2 R1 IN+ INGS VRef VSS X-tal OSC1 OSC2 NC NC DTMF OUTPUT RL TONE R/W/WR CS VDD St/GT ESt D3 D2 D1 D0 NC PWDN IRQ/CP DS/RD RS0 To P or C R3 C2 R4 C3
Notes: R1, R2 = 100 k 1% R3 = 374 1% R4 = 3.3 k 10% RL = 10 k (min.) C1 = 100 nF 5% C2 = 100 nF 5% C3 = 100 nF 10%* X-tal = 3.579545 MHz
* Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT8885 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided.
Figure 13 - Application Circuit (Single-Ended Input)
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MT8885
INITIALIZATION PROCEDURE A software reset must be included at the beginning of all programs to initialize the control registers after power up. Description: 1) 2) 3) 4) 5) 6) Read Status Register Write to Control Register Write to Control Register Write to Control Register Write to Control Register Read Status Register RS0 1 1 1 1 1 1 Intel Motorola WR RD R/W 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 1 1 0 Data b2 X 0 0 0 0 X
b3 X 0 0 1 0 X
b1 X 0 0 0 0 X
b0 X 0 0 0 0 X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones. Sequence: RS0 1) Write to Control Register A 1 (tone out, DTMF, IRQ, Select Control Register B) 2) Write to Control Register B 1 (burst mode) 3) Write to Transmit Data Register 0 (send a digit 7) 4) Wait for an Interrupt or Poll Status Register 5) Read the Status Register 1 R/W 0 0 0 WR RD 0 1 0 0 1 1 b3 1 0 0 b2 1 0 1 b1 0 0 1 b0 1 0 1
1
1
0
X
X
X
X
-if bit 1 is set, the Tx is ready for the next tone, in which case ... Write to Transmit Register 0 0 0 (send a digit 5) -if bit 2 is set, a DTMF tone has been received, in which case .... Read the Receive Data Register 0 1 1 -if both bits are set ... Read the Receive Data Register Write to Transmit Data Register
1
0
1
0
1
0
X
X
X
X
0 0
1 0
1 0
0 1
X 0
X 1
X 0
X 1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( 2 ms) AFTER THE DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms ( 4 ms)
Figure 14 - Application Notes
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MT8885
Absolute Maximum Ratings*
Parameter 1 2 3 4 5 Power supply voltage VDD-VSS Voltage on any pin Current at any pin (Except VDD and VSS) Storage temperature Package power dissipation Symbol VDD VI TST PD
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Min
Max 6
Units V V mA C mW
VSS-0.3 -65
VDD+0.3 10 +150 1000
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter 1 2 3 Positive power supply Operating temperature Crystal clock frequency Sym VDD TO fCLK Min 4.75 -40 3.575965 3.579545 Typ 5.00 Max 5.25 +85 3.583124 Units V C MHz Test Conditions
Typical figures are at 25 C and for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14
D i g i t a l Data Bus ESt and St/GT IRQ/ CP O U T P U T S S U P I N P U T S
VSS=0 V.
Sym VDD IDD VIHO VILO VTSt VOLO VOHO IOZ VRef ROR VIL VIH IIZ
Min 4.75
Typ 5.0 7.0 25
Max 5.25 11 A
Units V mA
Test Conditions
Operating supply voltage Operating supply current Standby supply current High level input voltage (OSC1) Low level input voltage (OSC1) Steering threshold voltage Low level output voltage (OSC2) High level output voltage (OSC2) Output leakage current (IRQ) VRef output voltage VRef output resistance Low level input voltage High level input voltage Input leakage current
PWDN= VDD V Note 9* Note 9* VDD=5V No load Note 9* No load Note 9* VOH=2.4 V No load, VDD=5V
3.5 1.5 2.2 2.3 2.5 0.1 4.9 1 2.4 2.5 1.3 0.8 2.0 10 10 2.6
V V V V A V k V V A
VIN=VSS to VDD
15 16 17 18 19
Source current Sink current Source current Sink current Sink current
IOH IOL IOH IOL IOL
-1.4 2.0 -0.5 2 4
-6.6 4.0 -3.0 4 16
mA mA mA mA mA
VOH=2.4V VOL=0.4V VOH=4.6V VOL=0.4V VOL=0.4V
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25 C, VDD =5V and for design aid only: not guaranteed and not subject to production testing. * See "Notes" following AC Electrical Characteristics Tables. 4-64
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MT8885
Electrical Characteristics Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V, VDD=5V, TO=25C.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 Input leakage current Input resistance Input offset voltage Power supply rejection Common mode rejection DC open loop voltage gain Unity gain bandwidth Output voltage swing Allowable capacitive load (GS) Allowable resistive load (GS) Common mode range Sym IIN RIN VOS PSRR CMRR AVOL BW VO CL RL VCM Min Typ 100 10 25 60 60 65 1.5 4.5 100 50 3.0 Max Units nA M mV dB dB dB MHz Vpp pF k Vpp No Load RL 100 k to VSS 1 kHz 0.75 VIN 4.25V Test Conditions VSS VIN VDD
Typical figures are at 25C and for design aid only: not guaranteed and not subject to production testing.
MT8885 AC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 R X Valid input signal levels (each tone of composite signal) Sym Min -29 27.5 Typ Max +1 869 Units dBm mVRMS Notes* 1,2,3,5,6 1,2,3,5,6
Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13.
AC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 R X Positive twist accept Negative twist accept Freq. deviation accept Freq. deviation reject Third tone tolerance Noise tolerance Dial tone tolerance 1.5% 2Hz 3.5% -16 -12 22 dB dB dB Sym Min Typ Max 8 8 Units dB dB
fC=3.579545 MHz
Notes* 2,3,6,9 2,3,6,9 2,3,5 2,3,5 2,3,4,5,9,10 2,3,4,5,7,9,10 2,3,4,5,8,9
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing. * *See "Notes" following AC Electrical Characteristics Tables.
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MT8885
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AC Electrical Characteristics- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics 1 2 3 4 Accept Bandwidth Lower freq. (REJECT) Upper freq. (REJECT) Call progress tone detect level (total power) Sym fA fLR fHR -30 Min 310 290 540 Typ Max 500 Units Hz Hz Hz dBm Conditions @ -25 dBm, Note 9 @ -25 dBm @ -25 dBm
Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics- DTMF Reception - Typical DTMF tone accept and reject requirements.
values are user selectable as per Figures 5, 6 and 7.
Actual
Characteristics 1 2 3 4 Minimum tone accept duration Maximum tone reject duration Minimum interdigit pause duration Maximum tone drop-out duration
Sym tREC tREC tID tOD
Min
Typ 40 20 40 20
Max
Units ms ms ms ms
Conditions
Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
X T A L T O N E O U T T O N E I N
Sym tDP tDA tPStb3 tPStRX tBST tPS tBSTE tPSE VHOUT VLOUT dBP THD
Min 3 0.5
Typ 11 4 13 8
Max 14 8.5
Units ms ms s s
Conditions Note 11 Note 11 See Figure 7 See Figure 7 DTMF mode DTMF mode Call Progress mode Call Progress mode RL=10k RL=10k RL=10k 25 kHz Bandwidth RL=10k
Tone present detect time Tone absent detect time Delay St to b3 Delay St to RX0-RX3 Tone burst duration Tone pause duration Tone burst duration (extended) Tone pause duration (extended) High group output level Low group output level Pre-emphasis Output distortion (Single Tone)
50 50 100 100 -6.1 -8.1 0 2 -35
52 52 104 104 -2.1 -4.1 3
ms ms ms ms dBm dBm dB dB
Frequency deviation Output load resistance Crystal/clock frequency Clock input rise and fall time Clock input duty cycle Capacitive load (OSC2)
fD RLT fC tCLRF DCCL CLO 40 10 3.5759
0.7
1.5 50
% k MHz ns % pF
fC=3.579545 MHz
3.5795
3.5831 110
Ext. clock Ext. clock
50
60 30
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and for design aid only: not guaranteed and not subject to production testing. 4-66
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MT8885
AC Electrical Characteristics- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DS/RD/WR clock frequency DS/RD/WR cycle period DS/RD/WR low pulse width DS/RD/WR high pulse width DS/RD/WR rise and fall time R/W setup time R/W hold time Address setup time (RS0) Address hold time (RS0) Data hold time (read) DS/RD to valid data delay (read) Data setup time (write) Data hold time (write) Chip select setup time Chip select hold time Input Capacitance (data bus) Output Capacitance (IRQ/CP) Sym fCYC tCYC tCL tCH tR,tF tRWS tRWH tAS tAH tDHR tDDR tDSW tDHW tCSS tCSH CIN COUT 45 10 45 40 5 5 35 23 20 0 40 22 100 20 150 100 20 Min Typ 4.0 250 Max Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF Conditions Figure 15 Figure 15 Figure 15 Figure 15 Figure 15 Figures 16 & 17 Figures 16 & 17 Figures 16 - 19 Figures 16 - 19 Figures 16 - 19 Figures 16 - 19 Figures 16 - 19 Figures 16 - 19 Figures 16 - 19 Figures 16 - 19
Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load. 2) Digit sequence consists of all 16 DTMF tones. 3) Tone duration=40 ms. Tone pause=40 ms. 4) Nominal DTMF frequencies are used. 5) Both tones in the composite signal have an equal amplitude. 6) The tone pair is deviated by 1.5 %2 Hz. 7) Bandwidth limited (3 kHz) Gaussian noise. 8) The precise dial tone frequencies are 350 and 440 Hz (2 %). 9) Guaranteed by design and characterization. Not subject to production testing. 10) Referenced to the lowest amplitude tone in the DTMF signal. 11) For guard time calculation purposes.
tCYC tR
DS/RD/WR
tF tCH tCL
Figure 15 - DS/RD/WR Clock Pulse
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MT8885
tRWS
DS
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tRWH
Q clk*
A0-A15 (RS0) R/W(read)
16 bytes of Addr
tDDR
Read Data (D3-D0)
tDHR
R/W (write)
tDSW
Write data (D3-D0)
tDHW
tCSS tAH
CS = (E + Q).Addr [MC6809] CS = VMA.Addr [MC6800, MC6802] *microprocessor pin
tCSH
tAS tAH tAS tCSS tCSH
Figure 16 - MC6800/MC6802/MC6809 Timing Diagram
tDSW is from data to DS falling edge; t CSH is from DS rising edge to CS rising edge.
tRWS
DS
tRWH
R/W
tAS
Read AD3-AD0 (RS0, D0-D3) Write AD3-AD0 (RS0-D0-D3) Addr
tDDR
tDHR
Data
Addr
Data
tDSW tAH tCSH
High Byte of Addr
tDHW
Addr * non-mux
AS *
CS = AS.Addr
tCSS
* microprocessor pins
Figure 17 - MC68HC11 Bus Timing (with multiplexed address and data buses)
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MT8885
tCSS
ALE*
RD
tAS
P0* (RS0, D0-D3) P2 * (Addr)
tAH
A0-A7
tDDR
Data
tDHR
A8-A15 Address
tCSH
CS = ALE.Addr
* microprocessor pins
Figure 18 - 8031/8051/8085 Read Timing Diagram
ALE*
tCSS
WR
tAS
P0* (RS0, D0-D3) P2 * (Addr)
tAH
A0-A7
tDSW tDHW
Data
A8-A15 Address
tCSH
CS = ALE.Addr
* microprocessor pins
Figure 19 - 8031/8051/8085 Write Timing Diagram
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MT8885
NOTES:
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